Modern electronic devices typically comprise a plurality of integrated circuits which are implemented on a wafer. Furthermore, system-in-package SiP devices comprise a plurality of dies stacked on top of each other. These dies need to be electrically interconnected. This is typically performed by means of through wafer holes or via interconnects which can be filled with Cu. The system-in-package devices may comprise elements or units from different technologies like passive dies in combination with a video processor, DSP co-processor, MEMS dies, transceivers, memories and graphic dies in silicon as well as in GaAS. Here, three dimensional interconnects are required. These interconnections may comprise vias that are filled with electrically conductive material. However, it should be noted that these vias have not been able to cater for different requirements, i.e. the vias must be insulated from the semiconductor substrate, and the conductor fillings of the via must be of the highest conductivity for most RF applications. Copper has a resistivity below 2 μΩ.cm and is therefore often used. The position of the copper is typically performed by electro-plating on a conductive seed layer. The width of the vias can range from 10 to 100 μm according to the application. The depths of the vias are usually between 100 and 300 μm.
FIG. 1 shows a schematic representation of a method of filing vias with Cu according to the prior art. Here, vias 110 are etched completely through the silicon layer 100. Thereafter, the vias 110 in the silicon layer is sealed by a sealing layer 120 at the back side of the wafer. Thereafter, the via is filled by bottom-up electro-plating. This can be started at the sealing layer 120. After the filling process, the via hole 110 is filled with copper Cu 130.
However, it should be noted that the sealing step of the via holes 110 is a critical step. Preferably, all vias should be sealed identically and the sealing should be performed at the same time in order to guarantee a uniformity of the bottom-up plating. Moreover, the sealing must exclude voids for a good electrical contact. The electro-chemical plating can result to a formation of copper bumps while other vias are not completely filled if the sealing has not been performed uniformly and at a controlled depth. In addition, any overgrowth of copper should be reduced on the back side of the wafer in order to prevent additional steps of a Cu removal.
FIG. 2 shows a representation of an alternative via sealing method according to the prior art. Here, PMMA polymer bridges are used to cap the via holes 110. In step a), an oxide layer 150 is provided on top of the silicon substrate. In step b), part of the oxide 150 is etched and in step c), a via hole 110 is etched partly into the silicon layer 100. In step d), an oxide layer 150 is deposited in the via hole 100. In step e), a PMMA layer 160 is provided on top of the oxide layer 150, wherein the PMMA 160 creates a bridge over the via hole 110. The PMMA 160 can be deposited by conventional spinning In step f), the access PMMA 160 is removed with chemical mechanical polishing. In step g), a seed layer Ti/Cu is deposited on the PMMA bridge. In step i), the PMMA bridge is removed and a free standing conductive membrane is provided over the via. In steps j) and k), the via hole is filled with copper.
However, it should be noted that a plurality of process steps are required. One critical point can be the chemical mechanical polishing CMP step to remove the PMMA in particular for thinned wafers. The risk of breaking the wafer is high and such a process is not cost effective.
FIG. 3 shows an alternative plating method according to the prior art. Here, a global sealing by means of a direct electro-plating on a Cu seed layer is described. The deposition of the seed layer 101 can be performed by conventional physical vapour deposition PVD. Here, the seed layer 101 only covers the top of the via 110 as the physical vapour deposition PVD merely has a low step coverage. Vias can be sealed by directly plating on the seed layer 101. The copper Cu can also grow inside the via 110 and on the field of the wafer. The via can be closed after sufficient plating time. However, it should be noted that this technique is very slow as a huge area needs to be plated. In addition, this process is very costly. Moreover, the thickness of the Cu layer is approx. 40 μm. Furthermore, this layer must be deposited on the side of the wafer in order to close the via. Moreover, it needs to be removed afterwards for example by means of chemical mechanical polishing.
Alternatively, resist trenches 103 can be provided and can be used to perform the Cu plating. Here, the thickness of the Cu layer can be reduced but is still approx. 30 μm. In addition, extra process steps like Cu grinding, chemical mechanical polishing, etc. need to be performed to remove the overfilling of the via holes. In addition, the wafer breakage during the handling is high and the costs are also high.
Finally, the wafer must be flipped over in order to perform a bottom-up electro-plating to complete the filling of the via holes. Accordingly, an extra handling step is required.
In “Reducing the Electro deposition Time for Filling Microvias with Copper for 3D Technology”, by Lühn et al., in IEEE Electronic Components and Technology Conference 2008 methods for reducing the electro-deposition time for filling vias are described.